128Mb: 8 Meg x 16 Mobile DDR SDRAM
Features
Mobile DDR SDRAM
MT46H8M16LF – 2 Meg x 16 x 4 Banks
For the latest data sheet, refer to Micron’s Web site: www.micron.com
Features
Figure 1:
• VDD/VDDQ = +1.8V ±0.1V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• Four internal banks for concurrent operation
• Data masks (DM) for masking write data–one mask
per byte
• Programmable burst lengths: 2, 4, or 8
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS-compatible inputs
• On-chip temperature sensor to control refresh rate
• Partial array self refresh (PASR)
• Selectable output drive (DS)
• Clock stop capability
Options
• VDD/VDDQ
• 1.8V/1.8V
• Configuration
• 8 Meg x 16 (2 Meg x 16 x 4 banks)
• Plastic package
• 60-Ball VFBGA (lead-free)
8mm x 10mm
• Timing – cycle time
• 7.5ns @ CL = 3
• 10ns @ CL = 3
• Operating temperature range
• Commercial (0° to +70°C)
• Industrial (-40°C to +85°C)
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
60-Ball VFBGA Assignment
(Top View)
1
2
3
VSS
DQ15
VDDQ
4
5
6
7
8
9
VSSQ
VDDQ
DQ0
VDD
DQ13
DQ14
DQ1
DQ2
VSSQ
VSSQ
DQ11
DQ12
DQ3
DQ4
VDDQ
VDDQ
DQ9
DQ10
DQ5
DQ6
TEST1
VSSQ
UDQS
DQ8
DQ7
LDQS
VDDQ
VSS
UDM
NC
NC
LDM
VDD
CKE
CK
CK#
WE#
CAS#
RAS#
A9
A11
NC
CS#
BA0
BA1
A6
A7
A8
A10/AP
A0
A1
VSS
A4
A5
A2
A3
VDD
A
B
C
D
E
F
G
H
J
K
Notes:1.D9 should be connected to VSS or VSSQ in
normal operations.
Marking
Table 1:
Configuration Addressing
H
Architecture
8M16
8 Meg x 16
2 Meg x 16 x 4
4K
4K (A0–A11)
4 (BA0, BA1)
512K (A0–A8)
Configuration
Refresh count
Row addressing
Bank addressing
Column addressing
CF
-75
-10
Table 2:
None
IT
1
Key Timing Parameters
Clock Rate
Access Time
Speed
Grade
CL = 2
CL = 3
CL = 2
CL = 3
-75
-10
83 MHz
67 MHz
133 MHz
104 MHz
6.5ns
7.0ns
6.0ns
7.0ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Table of Contents
Table of Contents
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
FBGA Part Marking Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Standard Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Bank/row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 33:
Figure 34:
Figure 35:
Figure 36:
Figure 37:
Figure 38:
Figure 39:
Figure 40:
Figure 41:
Figure 42:
Figure 43:
60-Ball VFBGA Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Functional Block Diagram (8 Meg x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Standard Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Clock Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK ≤ 3 . . . . . . . . . . . . . . . . . . . . . .20
READ Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
READ Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Consecutive WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Nonconsecutive WRITE-to-WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
WRITE-to-READ – Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
WRITE-to-READ – Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
WRITE-to-READ – Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
WRITE-to-PRECHARGE – Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
WRITE-to-PRECHARGE – Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
WRITE-to-PRECHARGE – Odd Number of Data, Interrupting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Power-Down Command (Active or Precharge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Typical Self-Refresh Current vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Data Output Timing – tAC and tDQSCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Initialize and Load Mode Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Power-Down Mode (Active or Precharge). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Bank Read – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Bank Read – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Bank Write – Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Bank Write – with Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Write – DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
60-Ball VFBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Configuration Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
128Mb Mobile DDR SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
60-Ball VFBGA Ball Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Truth Table – Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Truth Table – DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Truth Table – CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Truth Table – Current State Bank n - Command to Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Truth Table – Current State Bank n - Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Absolute Maximum DC Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
AC/DC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .50
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4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
FBGA Part Marking Decoder
Table 3:
128Mb Mobile DDR SDRAM Part Numbers
Part Number
MT46H8M16LFCF-75
MT46H8M16LFCF-75IT
MT46H8M16LFCF-10
MT46H8M16LFCF-10IT
Configuration
I/O Drive Level
Temperature Option
8 Meg x 16
8 Meg x 16
8 Meg x 16
8 Meg x 16
Programmable drive
Programmable drive
Programmable drive
Programmable drive
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part
marking that is different from the part number. Micron’s new FBGA Part Marking
Decoder makes it easier to understand this part marking. Visit the Web site at
www.micron.com/decoder.
General Description
The 128Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access
memory containing 134,271,728 bits. It is internally configured as a quad-bank DRAM.
Each of the 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits.
The 128Mb Mobile DDR SDRAM uses a double data rate architecture to achieve highspeed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O
balls. A single read or write access for the 128Mb DDR SDRAM effectively consists of a
single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O balls.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the Mobile DDR SDRAM
during READs and by the memory controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs. The x16 offering has two data
strobes, one for the lower byte and one for the upper byte.
The 128Mb Mobile DDR SDRAM operates from a differential clock (CK and CK#); the
crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of
CK. Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
Read and write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at
a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed.
The address bits registered coincident with the READ or WRITE command are used to
select the bank and the starting column location for the burst access.
The Mobile DDR SDRAM provides for programmable READ or WRITE burst lengths of 2,
4, or 8. An auto precharge function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
As with standard SDR SDRAMs, the pipelined, multibank architecture of Mobile DDR
SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by
hiding row precharge and activation time.
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5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
General Description
An auto-refresh mode is provided, along with a power saving power-down mode. Self
refresh mode offers temperature compensation through an on-chip temperature sensor
and partial array self refresh, which allow users to achieve additional power saving. The
temperature sensor is enabled by default and the partial array self refresh can be
programmed through the extended mode register.
Notes:
1. Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is divided into two bytes—the lower byte and upper byte.
For the lower byte (DQ0–DQ7) DM refers to LDM and DQS refers to LDQS; and for the
upper byte (DQ8–DQ15) DM refers to UDM and DQS refers to UDQS.
2. Complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all
requirements.
3. Any specific requirement takes precedence over a general statement.
Figure 2:
Functional Block Diagram (8 Meg x 16)
CKE
CK#
CK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
REFRESH
COUNTER
12
STANDARD MODE
REGISTER
EXTENDED MODE
REGISTER
ROWADDRESS
MUX
14
12
12
BANK0
ROWADDRESS
4,096
LATCH
AND
DECODER
BANK0
MEMORY
ARRAY
(4,096 x 256 x 32)
DATA
16
32
READ
LATCH
SENSE AMPLIFIERS
16
MUX
DRVRS
16
2
DQS
GENERATOR
8,192
DQ0–
DQ15
COL0
I/O GATING
DM MASK LOGIC
2
A0–A11,
BA0, BA1
14
ADDRESS
REGISTER
2
32
BANK
CONTROL
LOGIC
COLUMN
DECODER
COLUMNADDRESS
COUNTER/
LATCH
DQS
INPUT
REGISTERS
2
2
2
2
16
16
16
16
MASK
256
(x32)
9
CK
8
32
WRITE
FIFO
&
DRIVERS
ck
out
ck
in
LDQS
UDQS
2
4
32
RCVRS
16
LDM,
UDM
DATA
CK
2
COL0
1
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6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Ball Description
Ball Description
Table 4:
60-Ball VFBGA Ball Description
Ball Numbers
Symbol
Type
Description
G2, G3
CK, CK#
Input
G1
CKE
Input
H7
CS#
Input
G9, G8, G7
Input
F2, F8
RAS#, CAS#,
WE#
UDM, LDM
H8, H9
BA0, BA1
Input
J8, J9, K7, K8, K2,
K3, J1, J2, J3, J7,
H1, H2
A0–A11
Input
A8, B7, B8, C7, C8,
D7, D8, E7 E3, D2,
D3, C2, C3, B2, B3,
A2
E2, E7
DQ0–DQ15
I/O
Clock: CK is the system clock input. CK and CK# are differential clock inputs.
All address and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of CK#. Input and output data is
referenced to the crossing of CK and CK# (both directions of the crossing).
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal
clock signals, input buffers, and output drivers. Taking CKE LOW allows
PRECHARGE power-down and SELF REFRESH operations (all banks idle), or
ACTIVE power-down (row active in any bank). CKE is synchronous for all
functions expect SELF REFRESH exit. All input buffers (except CKE) are
disabled during power-down and self refresh modes.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH.
CS# provides for external bank selection on systems with multiple banks. CS#
is considered part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
Input data mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH along with that input data during a
WRITE access. DM is sampled on both edges of DQS. Although DM balls are
input-only, the DM loading is designed to match that of DQ and DQS balls.
For the x16, LDM is DM for DQ0–DQ7 and UDM is DM for DQ8–DQ15.
Bank address inputs: BA0 and BA1 define to which bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA0 and BA1 also
determine which mode register (standard mode register or extended mode
register) is loaded during a LOAD MODE REGISTER command.
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ or WRITE commands,
to select one location out of the memory array in the respective bank.
During a PRECHARGE command, A10 determines whether the PRECHARGE
applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10
HIGH). The address inputs also provide the op-code during a LOAD MODE
REGISTER command.
Data input/output: Data bus for x16.
UDQS, LDQS
I/O
VDDQ
VSSQ
VDD
VSS
Supply
Supply
Supply
Supply
Input
Input
A7, B1, C9, D1, E9
A3, B9, C1, E1
A9, F9, K9
A1, F1, K1
F3, F7, H3
D9
NC
TEST
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Input
Data strobe: Output with read data, input with write data. DQS is edgealigned with read data, centered in write data. It is used to capture data.
DQ power supply.
DQ ground: Isolated on the die for improved noise immunity.
Power supply.
Ground.
No connect. These pins should be left unconnected.
Test pin: Must be tied to VSS or VSSQ in normal operations.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Functional Description
Functional Description
The 128Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access
memory containing 134,271,728-bits. It is internally configured as a quad-bank DRAM.
Each of the 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits.
The 128Mb Mobile DDR SDRAM uses a double data rate architecture to achieve highspeed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O
balls. single read or write access for the 128Mb Mobile DDR SDRAM consists of a single
2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O balls.
Read and write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at
a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed
(BA0, BA1 select the bank; A0–A11 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the starting column location for
the burst access.
It should be noted that the DLL that is typically used on standard DDR devices is not
necessary on the Mobile DDR SDRAM. It has been omitted to save power.
Prior to normal operation, the Mobile DDR SDRAM must be initialized. The following
sections provide detailed information covering device initialization, register definition,
command descriptions and device operation.
Initialization
Mobile DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation.
If there is an interruption to the device power, the initialization routine should be
followed to ensure proper functionality of the Mobile DDR SDRAM.
To properly initialize the Mobile DDR SDRAM, the following sequence must be followed:
1. It is recommended the core power (VDD) and I/O power (VDDQ) be from the same
power source and brought up simultaneously. If separate power sources are used, VDD
must lead VDDQ.
2. Once power supply voltages are stable and the CKE has been driven HIGH, it is safe to
apply the clock.
3. Once the clock is stable, a 200µs minimum delay is required by the Mobile DDR
SDRAM prior to applying an executable command. During this time, NOP or DESELECT commands must be issued on the command bus.
4. Issue a PRECHARGE ALL command.
5. Issue NOP or DESELECT commands for at least tRP time.
6. Issue an AUTO REFRESH command followed by NOP or DESELECT commands for at
least tRFC time. Issue a second AUTO REFRESH command followed by NOP or DESELECT commands for at least tRFC time. As part of the individualization sequence, two
AUTO REFRESH commands must be issued. Typically, both of these commands are
issued at this stage as described above. Alternately, the second AUTO-REFRESH command and NOP or DESELECT sequence can be issued after step 10.
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8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Register Definition
7. Using the LOAD MODE REGISTER command, load the standard mode register as
desired.
8. Issue NOP or DESELECT commands for at least tMRD time.
9. Using the LOAD MODE REGISTER command, load the extended mode register to the
desired operating modes. Note that the sequence in which the standard and extended
mode registers are programmed is not critical.
10. Issue NOP or DESELECT commands for at least tMRD time.
The Mobile DDR SDRAM has been properly initialized and is ready to receive any valid
command.
Register Definition
Mode Registers
The mode registers are used to define the specific mode of operation of the Mobile DDR
SDRAM. There are two mode registers used to specify the operational characteristics of
the device. The standard mode register, which exists for all SDRAM devices, and the
extended mode register, which is exists on all Mobile SDRAM devices.
Standard Mode Register
The standard mode register definition includes the selection of a burst length, a burst
type, a CAS latency and an operating mode, as shown in Figure 3 on page 10. The standard mode register is programmed via the LOAD MODE REGISTER command (with BA0
= 0 and BA1 = 0) and will retain the stored information until it is programmed again.
Reprogramming the standard mode register will not alter the contents of the memory,
provided it is performed correctly. The mode register must be loaded when all banks are
idle and no bursts are in progress, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements will result in
unspecified operation.
Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4–A6 specify the CAS latency, and A7–A11 specify the operating
mode.
Note:
Standard refers to meeting JEDEC-standard mode register definitions.
Burst Length
Read and write accesses to the Mobile DDR SDRAM are burst oriented, with the burst
length being programmable, as shown in Figure 3 on page 10. The burst length determines the maximum number of column locations that can be accessed for a given READ
or WRITE command. Burst lengths of 2, 4, or 8 are available for both the sequential and
the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap until a boundary is reached. The block is uniquely
selected by A1–Ai when BL = 2, by A2–Ai when BL = 4, by A3–Ai when BL = 8 (where Ai is
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9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Register Definition
the most significant column address bit for a given configuration). The remaining (least
significant) address bit(s) is (are) used to select the starting location within the block.
The programmed burst length applies to both READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type
and the starting column address. See Table 5 on page 11 for more information.
READ Latency
The READ latency is the delay, in clock cycles, between the registration of a READ
command and the availability of the first bit of output data. The latency can be set to 2 or
3 clocks, as shown in Figure 3 on page 10.
For CL = 3, if the READ command is registered at clock edge n, then the data will nominally be available at (n + 2 clocks + tAC). For CL = 2, if the READ command is registered at
clock edge n, then the data will be nominally be available at (n + 1 clock + tAC).
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
Figure 3:
Standard Mode Register Definition
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
A0
Address Bus
M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0
Should be
programmed
to “0” to ensure
compatibility with
future devices.
13 12
0
0
11
9
8
7
10
Operating Mode
0
6 5
4
3
2
1
CAS Latency BT Burst Length
Burst Length
M13 M12 Mode Register Definintion
0
0
Base Mode Register
M2 M1 M0
M3 = 0
M3 = 1
0
1
Reserved
0
0
0
Reserved
Reserved
1
0
Extended Mode Register
0
0
1
2
2
1
1
Resereved
0
1
0
4
4
0
1
1
8
8
Operating Mode
1
0
0
Reserved
Reserved
Normal Operation
1
0
1
Reserved
Reserved
All other states reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
M11 M10 M9
M8 M7
0
0
0
0
0
Valid
–
–
–
–
–
–
M6 M5 M4
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MT46H8M16LF_1.fm - Rev. K 7/07 EN
Mode
Register
CAS Latency
0
0
0
Reserved
0
0
1
Reserved
M3
0
1
0
2
0
Sequential
0
1
1
3
1
Interleaved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
10
Burst Type
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Register Definition
Table 5:
Burst Definition
Burst
Length
2
4
8
Figure 4:
Order of Accesses Within a Burst
Starting
Column Address
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
A1
0
0
1
1
A1
0
0
1
1
0
0
1
1
A2
0
0
0
0
1
1
1
1
Type = Sequential
Type = Interleaved
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
CAS Latency
T0
T1
READ
NOP
T1n
T2
T2n
T3
T3n
CK#
CK
COMMAND
NOP
NOP
tAC
1 clock
CL = 2
DQS
DQ
CK#
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
T2n
T3
T3n
T0
T1
T2
READ
NOP
NOP
CK
COMMAND
2 clock
NOP
tAC
CL = 3
DQS
DOUT
n
DQ
TRANSITIONING DATA
Notes:
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MT46H8M16LF_1.fm - Rev. K 7/07 EN
DOUT
n+1
DON’T CARE
1. BL = 4 in the cases shown.
2. Shown with nominal tAC and nominal tDSDQ.
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Register Definition
Operating Mode
The normal operating mode is selected by issuing a LOAD MODE REGISTER SET
command with bits A7–A11 each set to zero, and bits A0–A6 set to the desired values.
All other combinations of values for A7–A11 are reserved for future use and/or test
modes. Test modes and reserved states should not be used because unknown operation
or incompatibility with future versions may result.
Extended Mode Register
The extended mode register controls functions specific to low power operation. These
additional functions include drive strength, temperature compensated self refresh, and
partial array self refresh.
Temperature Compensated Self Refresh
On this version of the Mobile DDR SDRAM, a temperature sensor is implemented for
automatic control of the self refresh oscillator on the device. Programming of the
temperature compensated self refresh (TCSR) bits will have no effect on the device. The
self refresh oscillator will continue refresh at the factory programmed optimal rate for
the device temperature.
Partial Array Self Refresh
For further power savings during SELF REFRESH, the PASR feature allows the controller
to select the amount of memory that will be refreshed during SELF REFRESH. The
refresh options are as follows:
• Full array: banks 0, 1, 2, and 3
• Half array: banks 0 and 1
• Quarter array: bank 0
WRITE and READ commands can still occur during standard operation, but only the
selected banks will be refreshed during SELF REFRESH. Data in banks that are disabled
will be lost.
Output Driver Strength
Because the Mobile DDR SDRAM is designed for use in smaller systems that are mostly
point to point, an option to control the drive strength of the output buffers is available.
Drive strength should be selected based on the expected loading of the memory bus. Bits
A5 and A6 of the extended mode register can be used to select the driver strength of the
DQ outputs. There are three allowable settings for the output drivers (25 ohm internal
impedance, 55 ohm internal impedance, and 80 ohm internal impedance).
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Register Definition
Figure 5:
Extended Mode Register
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
A0
E13 E12 E11 E10 E9
E8
E7
E6
E0
13 12
1
0
8
7
6 5
DS
11
9
10
set to “0”
E13 E12 Mode Register Definintion
0 Base Mode Register
0
1 Reserved
0
0 Extended Mode Register
1
1 Reserved
1
E11 E10 E9
0
0
0
–
–
E8
0
E7
0
–
–
–
Notes:
E6–E0
Valid
–
E5
E4
E3
4
3
TCSR1
E2
2
E6
E5
Driver Strength
0
0
0
1
Full Strength Driver
Half Strength Driver
1
1
0
1
Quarter Strength Driver
Reserved
Operating Mode
Normal Operation
All other states reserved
E1
0
1
PASR
Address Bus
Extended Mode
Register
E2
0
0
E1
0
0
E0
0
1
Partial Array Self Refresh Coverage
Full Array (All Banks)
Half Array (BA1 = 0)
0
1
0
Quarter Array (BA1 = BA0 = 0)
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
1. On-chip temperature sensor is used in place of TCSR. Setting these bits will have no effect.
Stopping the External Clock
One method of controlling the power efficiency in applications is to throttle the clock
which controls the SDRAM. There are two basic ways to control the clock:
1. Change the clock frequency.
2. Stop the clock.
Both of these are specific to the application and its requirements and both allow power
savings due to possible less transitions on the clock path.
The Mobile DDR SDRAM allows the clock to change frequency during operation, only if
all the timing parameters are met with respect to that change and all refresh requirements are satisfied.
The clock can also be stopped if there are no data accesses in progress, either WRITEs or
READs that would be affected by this change. If a WRITE or a READ is in progress the
entire data burst must be complete prior to stopping the clock.
For READs, a burst completion is defined when the read postamble is satisfied; for
WRITEs, a burst completion is defined when the write postamble and tWR or tWTR are
satisfied. CKE must be held HIGH with CK = LOW and CK# = HIGH for the full duration
of the clock stop mode. One clock cycle and at least one NOP is required after the clock is
restarted before a valid command can be issued. Figure 6 on page 14 illustrates the clock
stop mode.
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Register Definition
Figure 6:
Clock Stop Mode
Ta1
CK#
CK
CKE
((
))
((
))
((
))
((
))
Address
((
))
((
))
High-Z
Tb3
((
))
((
))
COMMAND
DQ, DQS
Ta2
((
))
((
))
CMD2
NOP1
Valid
((
))
((
))
((
))
((
))
((
))
((
))
((
))
2
( ( CMD
))
((
))
((
))
Tb4
Valid
NOP
NOP
((
))
((
))
((
))
((
))
((
))
All DRAM activities must be complete3
Exit clock stop mode
Enter clock stop mode4
DON’T CARE
Notes:
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1. Prior to Ta1, the device is in clock stop mode. To exit, at least one NOP is required before
any valid command.
2. Any valid command is allowed, device is not in clock suspend mode.
3. Any DRAM operation already in process must be completed before entering clock stop
mode. This includes tRCD, tRP, tRFC, tMRD, tWR, all data-out for READ bursts.
4. To enter and maintain a clock stop mode: CK = LOW, CK# = HIGH, CKE = HIGH.
14
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Commands
Commands
Table 6 and Table 7 provide quick references of available commands. This is followed by
a written description of each command. Three additional Truth Tables (Table 8 on
page 42, Table 9 on page 43, and Table 10 on page 45) provide CKE commands and
current/next state information.
Table 6:
Truth Table – Commands
Note 1 applies to all commands; All states and sequences not shown are reserved and/or illegal.
Name (Function)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (deactivate row in bank or banks)
AUTO REFRESH (refresh all or single bank)
or SELF REFRESH (enter self refresh mode)
LOAD MODE REGISTER (standard or extended mode
registers)
Notes:
Table 7:
CS#
RAS#
CAS#
WE#
ADDR
Notes
H
L
L
L
L
L
L
L
X
H
L
H
H
H
L
L
X
H
H
L
L
H
H
L
X
H
H
H
L
L
L
H
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
9
9
3
4
4
8
5
6, 7
L
L
L
L
Op-Code
2
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. BA0–BA1 select either the standard mode register or the extended mode register
(BA0 = 0, BA1 = 0 select the standard mode register; BA0 = 1, BA1 = 0 select extended mode
register; other combinations of BA0–BA1 are reserved). A0–A11 provide the op-code to be
written to the selected mode register.
3. BA0–BA1 provide bank address and A0–A11 provide row address.
4. BA0–BA1 provide bank address; A0–A8 provide column address; A10 HIGH enables the auto
precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
5. A10 LOW: BA0–BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0–BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except
for CKE.
8. Applies only to READ bursts with auto precharge disabled; this command is undefined (and
should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.
9. DESELECT and NOP are functionally interchangeable.
Truth Table – DM Operation
Name (Function)
Write enable
Write inhibit
Note:
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DM
DQ
L
H
Valid
X
Used to mask write data; provided coincident with corresponding data.
15
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Commands
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the Mobile DDR SDRAM. The Mobile DDR SDRAM is effectively deselected. Operations
already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to
perform a NOP (CS# = LOW, RAS# = CAS# = WE# = HIGH). This prevents unwanted
commands from being registered during idle or wait states. Operations already in
progress are not affected.
LOAD MODE REGISTER
The mode registers are loaded via inputs A0–A11. See mode register descriptions in
“Register Definition” on page 9. The LOAD MODE REGISTER command can only be
issued when all banks are idle, and a subsequent executable command cannot be issued
until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address
provided on inputs A0–A11 selects the row. This row remains active (or open) for
accesses until a PRECHARGE command is issued to that bank. A PRECHARGE
command must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on
the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A8 selects
the starting column location. The value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row being accessed will be
precharged at the end of the READ burst; if auto precharge is not selected, the row will
remain open for subsequent accesses.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–Ai
(where i = 8 for x16) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being
accessed will be precharged at the end of the WRITE burst; if auto precharge is not
selected, the row will remain open for subsequent accesses. Input data appearing on the
DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be
written to memory; if the DM signal is registered HIGH, the corresponding data inputs
will be ignored, and a WRITE will not be executed to that byte/column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the precharge command is issued. Except in the case of
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Commands
concurrent auto precharge, where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer in the current bank and does
not violate any other timing parameters. Input A10 determines whether one or all banks
are to be precharged, and in the case where only one bank is to be precharged, inputs
BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank
has been precharged, it is in the idle state and must be activated prior to any READ or
WRITE commands being issued to that bank. A PRECHARGE command will be treated
as a NOP if there is no open row in that bank (idle state), or if the previously open row is
already in the process of precharging.
Auto Precharge
Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished
by using A10 to enable auto precharge in conjunction with a specific READ or WRITE
command. A precharge of the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of the READ or WRITE burst.
Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. This device supports concurrent auto precharge if the
command to the other bank does not interrupt the data transfer to the current bank.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a
burst. This “earliest valid stage” is determined as if an explicit PRECHARGE command
was issued at the earliest possible time, without violating tRAS (MIN), as described for
each burst type in “Operations” on page 19. The user must not issue another command
to the same bank until the precharge time (tRP) is completed.
BURST TERMINATE
The BURST TERMINATE command is used to truncate READ bursts (with auto
precharge disabled). The most recently registered READ command prior to the BURST
TERMINATE command will be truncated, as shown in “Operations” on page 19. The
open page which the READ burst was terminated from remains open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the Mobile DDR SDRAM and is
analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in FPM/EDO DRAMs. This
command is nonpersistent, so it must be issued each time a refresh is required.
The addressing is generated by the internal refresh controller. This makes the address
bits a “Don’t Care” during an AUTO REFRESH command. The 128Mb Mobile DDR
SDRAM requires AUTO REFRESH cycles at an average interval of 15.625µs (maximum).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided.
Although not a JEDEC requirement, to provide for future functionality features, CKE
must be active (HIGH) during the auto refresh period. The auto refresh period begins
when the AUTO REFRESH command is registered and ends tRFC later.
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Commands
SELF REFRESH
The SELF REFRESH command can be used to retain data in the Mobile DDR SDRAM,
even if the rest of the system is powered down. When in the self refresh mode, the Mobile
DDR SDRAM retains data without external clocking. The SELF REFRESH command is
initiated like an AUTO REFRESH command except CKE is disabled (LOW). All command
and address input signals except CKE are “Don’t Care” during SELF REFRESH.
During SELF REFRESH, the device is refreshed as identified in the external mode register
(see PASR setting).
The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK
must be stable prior to CKE going back HIGH. Once CKE is HIGH, the Mobile DDR
SDRAM must have NOP commands issued for tXSR is required for the completion of any
internal refresh in progress.
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Operations
Bank/row Activation
Before any READ or WRITE commands can be issued to a bank within the Mobile DDR
SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE
command, which selects both the bank and the row to be activated, as shown in
Figure 7.
After a row is opened with an ACTIVE command, a READ or WRITE command may be
issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a tRCD specification of 20ns with a 133 MHz clock (7.5ns period)
results in 2.7 clocks rounded to 3. This is reflected in Figure 8 on page 20,which covers
any case where 2 < tRCD (MIN)/ tCK ≤ 3. (Figure 8 also shows the same case for tRCD; the
same procedure is used to convert other specification limits from time units to clock
cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
RRD.
Figure 7:
Activating a Specific Row in a Specific Bank
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A11
RA
BA0, BA1
BA
RA = Row Address
BA = Bank Address
DON’T CARE
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 8:
Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK ≤ 3
T0
T1
ACT
NOP
T2
T3
T4
T5
T6
T7
NOP
NOP
RD/WR
NOP
CK#
CK
COMMAND
A0-A11
BA0, BA1
NOP
Row
ACT
Row
Bank x
Col
Bank y
tRRD
Bank y
tRCD
DON’T CARE
READs
READ bursts are initiated with a READ command, as shown in Figure 9 on page 21.
The starting column and bank addresses are provided with the READ command and
auto precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is precharged at the completion of the burst. For the
READ commands used in the following illustrations, auto precharge is disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CAS latency after the READ command. Each subsequent dataout element will be valid nominally at the next positive or negative clock edge (i.e., at the
next crossing of CK and CK#). Figure 10 on page 22 shows general timing for each
possible CAS latency setting. DQS is driven by the Mobile DDR SDRAM along with
output data. The initial LOW state on DQS is known as the read preamble; the LOW state
coincident with the last data-out element is known as the read postamble.
Upon completion of a burst, assuming no other commands have been initiated, the DQs
will go High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out
window hold), the valid data window are depicted in Figure 31 on page 55. A detailed
explanation of tDQSCK (DQS transition skew to CK) and tAC (data-out transition skew to
CK) is depicted in Figure 32 on page 56.
Data from any READ burst may be concatenated with or truncated with data from a
subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a
completed burst or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles after the first READ
command, where x equals the number of desired data element pairs (pairs are required
by the 2n-prefetch architecture). This is shown in Figure 11 on page 23.
A READ command can be initiated on any clock cycle following a previous READ
command. Nonconsecutive read data is shown for illustration in Figure 12 on page 24.
Full-speed random read accesses within a page (or pages) can be performed, as shown
in Figure 13 on page 25.
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 9:
READ Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A9
CA
A11
EN AP
A10
DIS AP
BA0,1
BA
CA = Column Address
BA = Bank Address
EN AP = Enable Auto Precharge
DIS AP = Disable Auto Precharge
DON’T CARE
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 10:
READ Burst
T0
T1
READ
NOP
T1n
T2
T2n
T3
T3n
T4
T5
NOP
NOP
T4
T5
NOP
NOP
CK#
CK
COMMAND
ADDRESS
NOP
NOP
Bank a,
Col n
CL = 2
DQS
DOUT
n
DQ
T0
T1
T2
READ
NOP
NOP
DOUT
n+1
DOUT
n+2
DOUT
n+3
T2n
T3
T3n
CK#
CK
COMMAND
ADDRESS
NOP
Bank a,
Col n
CL = 3
DQS
DOUT
n
DQ
DOUT
n+1
DON’T CARE
Notes:
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DOUT
n+2
DOUT
n+3
TRANSITIONING DATA
1. DOUT n = data-out from column n.
2. BL = 4.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
22
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 11:
Consecutive READ Bursts
T0
T1
COMMAND
READ
NOP
ADDRESS
Bank,
Col n
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CK#
CK
READ
NOP
NOP
NOP
Bank,
Col b
CL = 2
DQS
DOUT
n
DQ
T0
T1
T2
COMMAND
READ
NOP
READ
ADDRESS
Bank,
Col n
DOUT
n+1
T2n
DOUT
n+2
DOUT
n+3
T3
DOUT
b
T3n
T4
DOUT
b+1
T4n
DOUT
b+2
DOUT
b+3
T5
T5n
CK#
CK
NOP
NOP
NOP
Bank,
Col b
CL = 3
DQS
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DON’T CARE
Notes:
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DOUT
n+3
DOUT
b
DOUT
b+1
TRANSITIONING DATA
1. DOUT n (or b) = data-out from column n (or column b).
2. BL = 4 in the cases shown (applies for bursts of 8 as well; if BL = 2, the BST command shown
can be a NOP).
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
4. This example represents consecutive READ commands issued to the device.
23
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 12:
Nonconsecutive READ Bursts
T0
T1
COMMAND
READ
NOP
ADDRESS
Bank,
Col n
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
CK#
CK
READ
NOP
NOP
NOP
NOP
Bank,
Col b
CL = 2
CL = 2
DQS
DOUT
n
DQ
T0
T1
COMMAND
READ
NOP
ADDRESS
Bank,
Col n
T1n
T2
DOUT
n+1
T2n
DOUT
n+2
T3
DOUT
n+3
T3n
DOUT
b
T4
T4n
T5
DOUT
b+1
T5n
DOUT
b+2
T6
CK#
CK
NOP
NOP
READ
NOP
NOP
Bank,
Col b
CL = 3
CL = 3
DQS
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
DON’T CARE
Notes:
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DOUT
b
TRANSITIONING DATA
1. DOUT n (or b) = data-out from column n (or column b).
2. BL = 4 in the cases shown (applies for bursts of 8 as well; if BL = 2, the BST command shown
can be a NOP).
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
4. This example represents nonconsecutive READ commands issued to the device.
24
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 13:
Random READ Accesses
T0
T1
T1n
T2
T2n
T3
COMMAND
READ
READ
READ
READ
ADDRESS
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
T3n
T4
T4n
T5
T5n
CK#
CK
NOP
NOP
CL = 2
DQS
DOUT
n
DQ
T0
T1
T1n
T2
DOUT
n+1
T2n
DOUT
x
DOUT
x+1
DOUT
b
DOUT
b+1
DOUT
g
T3
T3n
T4
T4n
T5
DOUT
g+1
T5n
CK#
CK
COMMAND
READ
READ
READ
READ
ADDRESS
Bank,
Col n
Bank,
Col x
Bank,
Col b
Bank,
Col g
NOP
NOP
CL = 3
DQS
DOUT
n
DQ
DOUT
n+1
DOUT
x
DON’T CARE
Notes:
DOUT
x+1
DOUT
b
DOUT
b+1
TRANSITIONING DATA
1. DOUT n (or x, b, g) = data-out from column n (or column x, column b, column g).
2. BL = 4 in the cases shown (applies for bursts of 8 as well; if BL = 2, the BST command shown
can be a NOP).
3. READs are to an active row in any bank.
4. Shown with nominal tAC, tDQSCK, and tDQSQ.
Truncated READs
Data from any READ burst may be truncated with a BURST TERMINATE command, as
shown in Figure 14 on page 26. The burst terminate latency is equal to the READ (CAS)
latency, i.e., the BURST TERMINATE command should be issued x cycles after the READ
command, where x equals the number of desired data element pairs (pairs are required
by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 15 on page 27. The tDQSS (MIN) case is shown; the
tDQSS (MAX) case has a longer bus idle time. (tDQSS [MIN] and tDQSS [MAX] are
defined in the section on WRITEs.)
A READ burst may be followed by, or truncated with, a PRECHARGE command to the
same bank provided that auto precharge was not activated. The PRECHARGE command
should be issued x cycles after the READ command, where x equals the number of
desired data element pairs (pairs are required by the n-prefetch architecture). This is
shown in Figure 16 on page 28. Following the PRECHARGE command, a subsequent
command to the same bank cannot be issued until tRP is met.
Note:
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Part of the row precharge time is hidden during the access of the last data elements.
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 14:
Terminating a READ Burst
T0
T1
T1n
T2
T2n
T3
T4
T5
NOP
NOP
NOP
T4
T5
NOP
NOP
CK#
CK
COMMAND
READ
ADDRESS
Bank a,
Col n
BST4
NOP
CL = 2
DQS
DOUT
n
DQ
T0
T1
T2
BST4
NOP
DOUT
n+1
T2n
T3
T3n
CK#
CK
COMMAND
READ
ADDRESS
Bank a,
Col n
NOP
CL = 3
DQS
DOUT
n
DQ
DOUT
n+1
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
1.
2.
3.
4.
5.
TRANSITIONING DATA
DOUT n = data-out from column n.
Only valid for BL = 4 and BL = 8.
Shown with nominal tAC, tDQSCK, and tDQSQ.
BST = BURST TERMINATE command; page remains open.
CKE = HIGH.
26
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 15:
READ-to-WRITE
T0
T1
COMMAND
READ
BST5
ADDRESS
Bank,
Col n
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CK#
CK
NOP
WRITE
NOP
NOP
Bank,
Col b
tDQSS
(NOM)
CL = 2
DQS
DQ
DOUT
n
DOUT
n+1
T2n
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
T4
T4n
T5
T5n
DM
T0
T1
T2
COMMAND
READ
BST5
NOP
ADDRESS
Bank,
Col n
T3
T3n
CK#
CK
NOP
WRITE
NOP
Bank,
Col b
tDQSS
(NOM)
CL = 3
DQS
DOUT
n
DQ
DOUT
n+1
DIN
b
DIN
b+1
DM
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
TRANSITIONING DATA
1. DOUT n = data-out from column n.
2. DIN b = data-in from column b.
3. BL = 4 in the cases shown (applies for bursts of 8 as well; if BL = 2, the BST command shown
can be a NOP).
4. Shown with nominal tAC, tDQSCK, and tDQSQ.
5. BST = BURST TERMINATE command; page remains open.
6. CKE = HIGH.
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 16:
READ-to-PRECHARGE
T0
T1
T1n
READ
NOP
T2
T2n
T3
T3n
T4
T5
NOP
ACT
CK#
CK
COMMAND5
ADDRESS
PRE
Bank a,
Col n
NOP
Bank a,
(a or all)
Bank a,
Row
tRP
CL = 2
DQS
DQ
T0
T1
READ
NOP
T1n
DOUT
n
DOUT
n+1
DOUT
n+2
T2
T2n
T3
DOUT
n+3
T3n
T4
T5
NOP
ACT
CK#
CK
COMMAND5
ADDRESS
PRE
NOP
Bank a,
(a or all)
Bank a,
Col n
Bank a,
Row
tRP
CL = 3
DQS
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
DOUT
n+3
TRANSITIONING DATA
1.
2.
3.
4.
5.
DOUT n = data-out from column n.
BL = 4 or an interrupted burst of 8.
Shown with nominal tAC, tDQSCK, and tDQSQ.
READ-to-PRECHARGE equals 2 clocks, which allows 2 data pairs of data-out.
A READ command with auto precharge enabled, provided tRAS (MIN) is met, would cause a
precharge to be performed at x number of clock cycles after the READ command, where x =
BL / 2.
6. PRE = PRECHARGE command; ACT = ACTIVE command.
28
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 17 on page 30.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the WRITE
commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on
DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first corresponding rising edge of DQS
(tDQSS) is specified with a relatively wide range (from 75 percent to 125 percent of one
clock cycle). All of the WRITE diagrams show the nominal case, and where the two
extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also
been included. Figure 18 on page 31 shows the nominal case and the extremes of tDQSS
for a burst of 4. Upon completion of a burst, assuming no other commands have been
initiated, the DQs will remain High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with or truncated with a subsequent
WRITE command. In either case, a continuous flow of input data can be maintained.
The new WRITE command can be issued on any positive edge of clock following the
previous WRITE command. The first data element from the new burst is applied after
either the last element of a completed burst or the last desired data element of a longer
burst which is being truncated. The new WRITE command should be issued x cycles
after the first WRITE command, where x equals the number of desired data element
pairs (pairs are required by the 2n-prefetch architecture).
Figure 19 on page 32 shows concatenated bursts of 4. An example of nonconsecutive
WRITEs is shown in Figure 20 on page 32. Full-speed random write accesses within a
page or pages can be performed, as shown in Figure 21 on page 33.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE without truncating the WRITE burst, tWTR should be met, as shown in Figure 22
on page 34.
Data for any WRITE burst may be truncated by a subsequent READ command, as shown
in Figure 23 on page 35. Note that only the data-in pairs that are registered prior to the
t
WTR period are written to the internal array, and any subsequent data-in should be
masked with DM, as shown in Figure 24 on page 36.
Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To
follow a WRITE without truncating the WRITE burst, tWR should be met, as shown in
Figure 25 on page 37.
Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as
shown in Figure 26 on page 38 and Figure 27 on page 39. Note that only the data-in pairs
that are registered prior to the tWR period are written to the internal array, and any
subsequent data-in should be masked with DM, as shown in Figure 26 on page 38 and
Figure 27 on page 39. After the PRECHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met.
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
29
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 17:
WRITE Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0–A8
CA
A11
EN AP
A10
DIS AP
BA0,1
BA
DON’T CARE
Note:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
DIS AP = Disable Auto Precharge
EN AP = Enable Auto Precharge
BA = Bank Address
CA = Column Address
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 18:
WRITE Burst
T0
T1
T2
COMMAND
WRITE
NOP
NOP
ADDRESS
Bank a,
Col b
T2n
T3
CK#
CK
tDQSS
NOP
(NOM)
DQS
tDQSS
DIN
b
DQ
DIN
b+2
DIN
b+1
DIN
b+3
DM
tDQSS
(MIN)
DQS
DQ
tDQSS
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b
DIN
b+1
DIN
b+2
DM
tDQSS
(MAX)
DQS
tDQSS
DQ
DIN
b+3
DM
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
TRANSITIONING DATA
1. DIN b = data-in for column b.
2. An uninterrupted burst of 4 is shown.
3. A10 is LOW with the WRITE command (auto precharge is disabled).
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 19:
Consecutive WRITE-to-WRITE
T0
T1
COMMAND
WRITE
NOP
ADDRESS
Bank,
Col b
T1n
T2
T2n
T3
T3n
T4
T4n
T5
CK#
CK
tDQSS (NOM)
WRITE
NOP
NOP
NOP
Bank,
Col n
tDQSS
DQS
DIN
b
DQ
DIN
b+1
DIN
b+2
DIN
b+3
DIN
n+1
DIN
n
DIN
n+2
DIN
n+3
DM
DON’T CARE
Notes:
Figure 20:
TRANSITIONING DATA
1. DIN b (n) = data-in for column b (n).
2. An uninterrupted burst of 4 is shown.
3. Each WRITE command may be to any bank.
Nonconsecutive WRITE-to-WRITE
T0
T1
COMMAND
WRITE
NOP
ADDRESS
Bank,
Col b
T1n
T2
T2n
T3
T4
T4n
T5
T5n
CK#
CK
tDQSS (NOM)
NOP
WRITE
NOP
NOP
Bank,
Col n
tDQSS
DQS
DQ
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
n
DIN
n+1
DIN
n+2
DIN
n+3
DM
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
TRANSITIONING DATA
1. DIN b (n) = data-in for column b (n).
2. An uninterrupted burst of 4 is shown.
3. Each WRITE command may be to any bank.
32
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 21:
Random WRITE Cycles
T0
T1
T1n
T2
T2n
T3
T3n
T4
COMMAND
WRITE
WRITE
WRITE
WRITE
WRITE
ADDRESS
Bank,
Col b
Bank,
Col x
Bank,
Col n
Bank,
Col a
Bank,
Col g
T4n
T5
T5n
CK#
CK
NOP
tDQSS (NOM)
DQS
DQ
Din
b
DIN
b'
DIN
x
DIN
x'
DIN
n
DIN
n'
DIN
a
DIN
a'
DIN
g
DIN
g'
DM
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
TRANSITIONING DATA
1. DIN b (or x, n, a, g) = data-in for column b (or x, n, q, g)
2. b' (or x, n, a, g) = the next data-in following DIN b (x, n, a, g), according to the programmed
burst order.
3. Programmed BL = 2, 4, or 8 in cases shown.
4. Each WRITE command may be to any bank.
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 22:
WRITE-to-READ – Uninterrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
READ
NOP
T5n
T6
T6n
CK#
CK
COMMAND
NOP
NOP
NOP
tWTR
Bank a,
Col b
ADDRESS
tDQSS (NOM)
Bank a,
Col n
tDQSS
CL = 2
DQS
DIN
b+1
DIN
b
DQ
DIN
b+2
DIN
b+3
DOUT
n
DOUT
n+1
DOUT
n
DOUT
n+1
DOUT
n
DOUT
n+1
DM
tDQSS (MIN)
tDQSS
CL = 2
DQS
DIN
b
DQ
DIN
b+1
DIN
b+2
DIN
b+3
DM
tDQSS (MAX)
tDQSS
CL = 2
DQS
DIN
b
DQ
DIN
b+1
DIN
b+2
DIN
b+3
DM
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
TRANSITIONING DATA
1.
2.
3.
4.
DIN b = data-in for column b; DOUT n = data-out for column n.
An uninterrupted burst of 4 is shown.
tWTR is referenced from the first positive CK edge after the last data-in pair.
The READ and WRITE commands are to same device. However, the READ and WRITE commands may be to different devices, in which case tWTR is not required and the READ command could be applied earlier.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 23:
WRITE-to-READ – Interrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
READ
NOP
NOP
T5n
T6
T6n
CK#
CK
COMMAND
NOP
NOP
tWTR
Bank a,
Col b
ADDRESS
tDQSS (NOM)
Bank a,
Col n
tDQSS
CL = 3
DQS
DIN
b+1
DIN
b
DQ
DOUT
n
DOUT
n+1
DM
tDQSS (MIN)
tDQSS
CL = 3
DQS
DIN
b
DQ
DOUT
n
DIN
b+1
DOUT
n+1
DM
tDQSS (MAX)
tDQSS
CL = 3
DQS
DIN
b
DQ
DIN
b+1
DOUT
n
DOUT
n+1
DM
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
1.
2.
3.
4.
5.
6.
TRANSITIONING DATA
DIN b = data-in for column b; DOUT n = data-out for column n.
An interrupted burst of 4 is shown; two data elements are written.
t
WTR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T2 and T2n (nominal case) to register DM.
If the burst of 8 was used, DM and DQS would be required at T3 and T3n because the READ
command would not mask these two data elements.
35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 24:
WRITE-to-READ – Odd Number of Data, Interrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
READ
NOP
NOP
T5n
T6
T6n
CK#
CK
COMMAND
NOP
NOP
tWTR
Bank a,
Col b
ADDRESS
tDQSS (NOM)
Bank a,
Col n
tDQSS
CL = 3
DQS
DOUT
n
DIN
b
DQ
DOUT
n+1
DM
tDQSS (MIN)
tDQSS
CL = 3
DQS
DOUT
n
DIN
b
DQ
DOUT
n+1
DM
tDQSS (MAX)
tDQSS
CL = 3
DQS
DIN
b
DQ
DOUT
n
DOUT
n+1
DM
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
1.
2.
3.
4.
5.
6.
TRANSITIONING DATA
DIN b = data-in for column b; DOUT n = data-out for column n.
An interrupted burst of 4 is shown; one data element is written, three are masked.
tWTR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
DQS is required at T2 and T2n (nominal case) to register DM.
If the burst of 8 was used, DM and DQS would be required at T3 and T3n because the READ
command would not mask these two data elements.
36
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 25:
WRITE-to-PRECHARGE – Uninterrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T4
T5
T6
NOP
PRE 6
NOP
CK#
CK
COMMAND
NOP
NOP
tWR
Bank a,
Col b
ADDRESS
tDQSS (NOM)
Bank
(a or all)
tDQSS
DQS
DIN
b+1
DIN
b
DQ
DIN
b+2
DIN
b+3
DM
tDQSS (MIN)
tDQSS
DQS
DIN
b
DQ
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b
DIN
b+1
DIN
b+2
DM
tDQSS (MAX)
tDQSS
DQS
DQ
DIN
b+3
DM
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
TRANSITIONING DATA
1.
2.
3.
4.
DIN b = data-in for column b.
An uninterrupted burst of 4 is shown.
tWR is referenced from the first positive CK edge after the last data-in pair.
The PRECHARGE and WRITE commands are to same device. However, the PRECHARGE and
WRITE commands may be to different devices, in which case tWR is not required and the
PRECHARGE command could be applied earlier.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
6. PRE = PRECHARGE command.
37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 26:
WRITE-to-PRECHARGE – Interrupting
CK#
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T6
NOP
NOP
CK
COMMAND
NOP
NOP
PRE 5
tWR
Bank a,
Col b
ADDRESS
tDQSS (NOM)
Bank
(a or all)
tDQSS
DQS
DIN
b
DQ
DIN
b+1
DM
tDQSS (MIN)
tDQSS
DQS
DIN
b
DQ
DIN
b+1
DM
tDQSS (MAX)
tDQSS
DQS
DIN
b
DQ
DIN
b+1
DM
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
1.
2.
3.
4.
5.
6.
7.
TRANSITIONING DATA
DIN b = data-in for column b.
An interrupted burst of 8 is shown.
tWR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
PRE = PRECHARGE command.
DQS is required at T4 and T4n (nominal case) to register DM.
If a burst of 4 was used, DQS and DM would not be required at T3, T3n, T4, and T4n.
38
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Figure 27:
WRITE-to-PRECHARGE – Odd Number of Data, Interrupting
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T6
CK#
CK
COMMAND
NOP
NOP
PRE7
tWR
Bank a,
Col b
ADDRESS
tDQSS (NOM)
NOP
NOP
tRP
Bank,
(a or all)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MIN)
tDQSS
DQS
DI
b
DQ
DM
tDQSS (MAX)
tDQSS
DQS
DI
b
DQ
DM
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
1.
2.
3.
4.
5.
6.
7.
TRANSITIONING DATA
DIN b = data-in for column b.
An interrupted burst of 8 is shown.
tWR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
PRE = PRECHARGE command.
DQS is required at T4 and T4n (nominal case) to register DM.
If a burst of 4 was used, DQS and DM would not be required at T3, T3n, T4, and T4n.
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
PRECHARGE
The PRECHARGE command (Figure 28) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row
access some specified time (tRP) after the PRECHARGE command is issued. Input A10
determines whether one or all banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank.
Figure 28:
PRECHARGE Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0-A9, A11
All
A10
Single
BA0,1
BA
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
1. BA = Bank Address.
All = All banks to be Precharged, BA1, BA0 are “Don't Care.”
Single = Only bank selected by BA1 and BA0 will be precharged.
40
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Operations
Power-Down
Power-down is entered when CKE is registered LOW. If power-down occurs when all
banks are idle, this mode is referred to as precharge power-down; if power-down occurs
when there is a row active in any bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and output buffers, including CK and CK#.
Exiting power-down requires the device to be at the same voltage as when it entered
power-down and a stable clock.
Note:
The power-down duration is limited by the refresh requirements of the device.
While in power-down, CKE LOW must be maintained at the inputs of the Mobile DDR
SDRAM, while all other input signals are “Don’t Care.” The power-down state is exited
when CKE is registered HIGH (in conjunction with a NOP or DESELECT command).
NOPs or DESELECT commands must be maintained on the command bus until tXP is
satisfied.
Figure 29:
Power-Down Command (Active or Precharge)
CK#
CK
CKE
CS#
RAS#, CAS#, WE#
OR
CS#
RAS#, CAS#, WE#
A0–A11
BA0–BA1
BA0,1
DON’T CARE
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Truth Tables
Truth Tables
Table 8:
Truth Table – CKE
Notes: 1–5
CKEn-1
CKEn
Current State
COMMANDn
ACTIONn
Notes
L
L
L
L
L
L
H
H
H
H
H
L
L
L
H
H
H
L
L
L
H
H
(Active) Power-Down
(Precharge) Power-Down
Self refresh
(Active) Power-Down
(Precharge) Power-Down
Self refresh
Bank(s) active
All banks idle
All banks idle
X
X
X
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
DESELECT or NOP
AUTO REFRESH
See Table 10 on page 45
See Table 10 on page 45
Maintain (active) power-down
Maintain (precharge) power-down
Maintain self refresh
Exit (active) power-down
Exit (precharge) power-down
Exit self refresh
(Active) power-down entry
(Precharge) power-down entry
Self refresh entry
6, 7
6, 7
8, 9
Notes:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock
edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of
COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. tCKE pertains.
6. DESELECT or NOP commands should be issued on any clock edges occurring during the tXP
period.
7. The clock must toggle at least once during the tXP period.
8. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSR
period.
9. The clock must toggle at least once during the tXSR period.
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Truth Tables
Table 9:
Truth Table – Current State Bank n - Command to Bank n
Notes: 1–6; notes appear below and on next page
Current State
CS#
RAS#
CAS#
WE#
Any
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
L
L
L
H
H
L
H
H
L
H
H
H
L
X
H
H
L
L
L
L
H
L
L
H
H
L
L
H
X
H
H
H
L
H
L
L
H
L
L
L
H
L
L
Idle
Row active
Read
(auto precharge
disabled)
Write
(auto precharge
disabled)
Notes:
Command/Action
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (truncate WRITE burst, start PRECHARGE)
Notes
7
7
10
10
8
10
10, 12
8
9
10, 11
10
8, 11
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tXSR has been met (if
the previous state was self refresh) and after tXP has been met (if the previous state was
power-down).
2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank
and the commands shown are those allowed to be issued to that bank when in that state).
Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row active: A row in the bank has been activated, and tRCD has been
met. No data bursts/accesses and no register accesses are in
progress.
Read: A READ burst has been initiated, with auto precharge
disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge
disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Table 9, and according to Table 10.
Precharging: Starts with registration of a PRECHARGE command and ends
when tRP is met. Once tRP is met, the bank will be in the idle
state.
Row activating: Starts with registration of an ACTIVE command and ends
when tRCD is met. Once tRCD is met, the bank will be in the
row active state.
Read w/auto- Starts with registration of a READ command with auto
precharge enabled: precharge enabled and ends when tRP has been met. Once
tRP is met, the bank will be in the idle state.
Write w/auto- Starts with registration of a WRITE command with auto
precharge enabled: precharge enabled and ends when tRP has been met. Once
tRP is met, the bank will be in the idle state.
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Truth Tables
5. The following states must not be interrupted by any executable command; DESELECT or
NOP commands must be applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and
ends when tRFC is met. Once tRFC is met, the DDR SDRAM
will be in the all banks idle state.
Accessing mode register: Starts with registration of a LOAD MODE REGISTER command
and ends when tMRD has been met. Once tMRD is met, the
Mobile DDR SDRAM will be in the all banks idle state.
Precharging all: Starts with registration of a PRECHARGE ALL command and
ends when tRP is met. Once tRP is met, all banks will be in the
idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a
valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of
bank.
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
precharge enabled and READs or WRITEs with auto precharge disabled.
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise,
a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE
command.
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Truth Tables
Table 10:
Truth Table – Current State Bank n - Command to Bank m
Notes: 1–6; notes appear below and on next page
Current State
CS#
RAS#
CAS#
WE#
Any
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
X
H
X
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
X
H
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
Idle
Row
activating,
active, or
precharging
Read
(auto precharge
disabled)
Write
(auto precharge
disabled)
Read
(with auto
precharge)
Write
(with auto
precharge)
Notes:
Command/Action
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command allowed to bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
Notes
7
7
7
7, 9
7, 8
7
7, 3a
7, 9, 3a
7, 3a
7, 3a
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH and after tXSR has been met (if
the previous state was self refresh) or after tXP has been met (if the previous state was
power-down).
2. This table describes alternate bank operation, except where noted (i.e., the current state is
for bank n and the commands shown are those allowed to be issued to bank m, assuming
that bank m is in such a state that given command is allowable). Exceptions are covered in
the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been
met. No data bursts/accesses and no register accesses are in
progress.
Read: A READ burst has been initiated, with auto precharge
disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge
disabled, and has not yet terminated or been terminated.
Read with auto precharge enabled: See following text – 3a
Write with auto precharge enabled: See following text – 3a
3a.
The read with auto precharge enabled or write with auto precharge enabled
states can each be broken into two parts: the access period and the precharge period. For
read with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For write with auto
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Truth Tables
precharge, the precharge period begins when tWR ends, with tWR measured as if auto precharge was disabled. The access period starts with registration of the command and ends
where the precharge period (or tRP) begins.
This device supports concurrent auto precharge such that when a read with auto
precharge enabled or a write with auto precharge is enabled any command to other banks
is allowed, long as that command does not interrupt the read or write data transfer already
in process. either case, all other related limitations apply (e.g., contention between read
data and write data must be avoided).
3b.
The minimum delay from a READ or WRITE command with auto precharge
enabled, to a command to a different bank is summarized below.
From Command
To Command
WRITE w/AP
READ or READ w/AP
WRITE or WRITE w/AP
PRECHARGE
ACTIVE
READ or READ w/AP
WRITE or WRITE w/AP
PRECHARGE
ACTIVE
READ w/AP
Minimum Delay
(with Concurrent Auto
Precharge)
[1 + (BL/2)] tCK + tWTR
(BL/2) tCK
1 tCK
1 tCK
(BL/2) × tCK
[CLRU + (BL/2)] tCK
1 tCK
1 tCK
CLRU = CAS latency (CL) rounded up to the next integer
BL = Bust length
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks
are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
precharge enabled and READs or WRITEs with auto precharge disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a
WRITE command.
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 11:
Absolute Maximum DC Ratings
Parameter
Symbol
Min
Max
Units
Notes
Vdd supply voltage relative to VSS
VddQ supply voltage relative to VSSQ
Voltage on any ball relative to VSS
VDD
VDDQ
VIN, VOUT
–1.0
–0.5
–0.5
2.3
2.3
2.3
V
V
V
1
1
2
Notes:
Table 12:
1. VDD, VDDQ, and VDDL must be within 300mV of each other at all times.
2. Voltage on any I/O may not exceed voltage on VDDQ.
AC/DC Electrical Characteristics and Operating Conditions
Notes: 1–5; notes appear on pages 52–54; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
Parameter/Condition
Supply voltage
I/O supply voltage
Address and Command Inputs
Input voltage high
Input voltage low
Clock Inputs (CK, CK#)
DC input voltage
DC input differential voltage
AC input differential voltage
AC differential crossing voltage
Data Inputs
DC input high voltage
AC input high voltage
DC input low voltage
AC input low voltage
Data Outputs
Symbol
Min
Max
Units
Notes
VDD
VDDQ
1.7
1.7
1.9
1.9
V
V
31
31
VIH
VIL
0.8 × VDDQ
VDDQ + 0.3
0.2 × VDDQ
V
V
25, 32
25, 32
VDDQ + 0.3
VDDQ + 0.3
VDDQ + 0.3
0.6 × VDDQ
V
V
V
V
27
8, 27
8, 27
9, 27
VDDQ + 0.3
VDDQ + 0.3
0.3 × VDDQ
0.2 × VDDQ
V
V
V
V
25, 28, 32
25, 28, 32
25, 28, 32
25, 28, 32
VIN
VID(DC)
VID(AC)
VIX
–0.3
0.4 × VDDQ
0.6 × VDDQ
0.4 × VDDQ
VIH(DC)
VIH(AC)
VIL(DC)
VIL(AC)
0.7 × VDDQ
0.8 × VDDQ
VOH
VOL
0.9 × VDDQ
–
–
0.1 × VDDQ
V
V
II
–1
1
µA
IOZ
–5
5
µA
DC output high voltage: Logic 1 (IOH = -0.1mA)
DC output low voltage: Logic 0 (IOL = 0.1mA)
Leakage Current
Input leakage current
Any input 0V ≤ VIN ≤ VDD
(All other balls not under test = 0V)
Output leakage current
(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)
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–0.3
47
–0.3
–0.3
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Electrical Specifications
Table 13:
Capacitance
Notes: 13; notes appear on pages 52–54
Parameter
Delta input/output capacitance: DQs, DQS, DM
Delta input capacitance: Command and address
Delta input capacitance: CK, CK#
Input/output capacitance: DQs, DQS, DM
Input capacitance: Address
Input capacitance: Command
Input capacitance: CK, CK#
Table 14:
Symbol
Min
Max
Units
Notes
CDIO
CDI
CDCK
CIO
CI
CI
CCK
–
–
–
3.0
1.5
1.5
1.5
1.00
1.75
0.25
5.5
4.0
5.0
4.5
pF
pF
pF
pF
pF
pF
pF
21
26
26
IDD Specifications and Conditions
Notes: 1–5, 7, 10, 12, 14 notes appear on pages 52–54; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
Max
Parameter/Condition
tRC
tRC
=
(MIN);
Operating one bank active precharge current:
= tCK (MIN); CKE is HIGH; CS is HIGH between valid commands;
Address inputs are switching every two clock cycles; Data bus inputs
are stable
Precharge power-down standby current: All banks idle; CKE is LOW; CS
is HIGH; tCK = tCK (MIN); Address and control inputs are switching
every two clock cycles; Data bus inputs are stable
Precharge power-down standby current with clock stopped: All banks
idle; CKE is LOW; CS is HIGH; CK = LOW, CK# = HIGH; Address and
control inputs are switching every two clock cycles; Data bus inputs
are stable
Precharge non power-down standby current: All banks idle;
CKE = HIGH; CS = HIGH; tCK = tCK (MIN); Address and control inputs
are switching every two clock cycles; Data bus inputs are stable
Precharge non power-down standby current: Clock stopped; All banks
idle; CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH Address and
control inputs are switching every two clock cycles; Data bus inputs
are stable
Active power-down standby current: One bank active; CKE = LOW;
CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching
every two clock cycles; Data bus inputs are stable
Active power-down standby current: Clock stopped; One bank active;
CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address and control
inputs are switching every two clock cycles; Data bus inputs are stable
Active non power-down standby: One bank active; CKE = HIGH;
CS = HIGH; tCK = tCK (MIN); Address and control inputs are switching
every two cycles; Data bus inputs are stable
Active non-power-down standby: Clock stopped; One bank active;
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and control
inputs are switching every two clock cycles; Data bus inputs are stable
Operating burst read: One bank active; BL = 4; tCK = tCK (MIN);
Continuous read bursts; IOUT = 0mA; Address inputs are switching;
50% data changing each burst
Operating burst write: One bank active; BL = 4; tCK = tCK (MIN);
Continuous WRITE bursts; Address inputs are switching; 50 percent
data changing each burst
Symbol
-75
-10
Units
Notes
IDD0
80
75
mA
19
IDD2P
200
200
µA
20, 28
IDD2PS
200
200
µA
20, 28
IDD2N
25
25
mA
34
IDD2NS
15
15
mA
34
IDD3P
3
3
mA
20, 28
IDD3PS
3
3
mA
20, 28
IDD3N
25
25
mA
19
IDD3NS
20
20
mA
19
IDD4R
95
90
mA
19
IDD4W
95
90
mA
19
tCK
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Electrical Specifications
Table 14:
IDD Specifications and Conditions (continued)
Notes: 1–5, 7, 10, 12, 14 notes appear on pages 52–54; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
Max
Parameter/Condition
Auto refresh: Burst refresh; CKE = HIGH; Address
and control inputs are switching; Data bus inputs
are stable
Precharge power-down standby current: All banks
idle, CKE is LOW; CS is HIGH; tCK = tCK (MIN);
address and data bus inputs are stable
Self refresh: CKE = LOW; tCK = tCK (MIN); Address
and control inputs are stable; Data bus inputs are
stable
Figure 30:
Symbol
-75
-10
Units
Notes
RC = RC (MIN)
IDD5
105
100
mA
35
RC = 15.625µs
IDD5a
5
5
mA
24, 35
Full Array, 85°C
Full Array, 70°C
Full Array, 45°C
Full Array 15°C
Half Array, 85°C
Half Array, 70°C
Half Array, 45°C
Half Array, 15°C
1/4 Array, 85°C
1/4 Array, 70°C
1/4 Array, 45°C
1/4 Array, 15°C
IDD6a
IDD6b
IDD6c
IDD6d
IDD6a
IDD6b
IDD6c
IDD6d
IDD6a
IDD6b
IDD6c
IDD6d
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
11, 36
11, 36
11, 36
11, 36
11, 36
11, 36
11, 36
11, 36
11, 36
11, 36
11, 36
11, 36
t
t
t
300
220
180
160
220
180
160
150
180
160
150
145
Typical Self-Refresh Current vs. Temperature
250.00
Current (uA)
200.00
150.00
Full Array
Half Array
Quarter Array
100.00
50.00
0.00
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
Temperature (C)
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Electrical Specifications
Table 15:
Electrical Characteristics and Recommended AC Operating Conditions
Notes: 1–6, 27; notes appear on pages 52–54; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
-75
Parameter
Access window of DQs from CK/CK#
Clock cycle time
Symbol
CL = 3
CL = 2
CL = 3
CL = 2
CK high-level width
CK low-level width
Minimum tCKE HIGH/LOW time
Auto precharge write recovery + precharge time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high-pulse width
DQS input low-pulse width
DQS–DQ skew, DQS to last DQ valid, per group,
per access
WRITE command to first DQS latching transition
DQS falling edge from CK rising – hold time
DQS falling edge to CK rising – setup time
Data valid output window (DVW)
Half-clock period
CL = 3
Data-out High-Z window from CK/CK#
CL = 2
Data-out Low-Z window from CK/CK#
Address and control input hold time
(fast slew rate)
Address and control input hold time
(slow slew rate)
Address and control input setup time
(fast slew rate)
Address and control input setup time
(slow slew rate)
Address and control input pulse width
LOAD MODE REGISTER command cycle time
DQ–DQS hold, DQS to first DQ to go non-valid,
per access
Data hold skew factor
ACTIVE-to-PRECHARGE command
ACTIVE-to-ACTIVE/AUTO REFRESH command
period
ACTIVE-to-READ or WRITE delay
Average periodic refresh interval
AUTO REFRESH command period
PRECHARGE command period
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Min
t
AC(3)
AC(2)
t
CK(3)
t
CK(2)
t
CH
t
CL
t
CKE
tDAL
t
DH
tDS
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDSH
tDSS
na
tHP
tHZ(3)
tHZ(2)
tLZ
tIH
F
Max
Min
Max
2.5
6.0
2.0
6.5
7.5
–
12
–
0.45
0.55
0.45
0.55
2
–
–
–
0.75
–
0.75
–
tDS + tDH
2.5
6.0
0.4
0.6
0.4
0.6
–
0.6
2.0
7.0
2.0
7.0
9.6
–
15
–
0.45
0.55
0.45
0.55
2
–
–
–
1.1
–
1.1
–
tDS + tDH
2.5
7.0
0.4
0.6
0.4
0.6
–
0.7
0.75
1.25
0.2
–
0.2
–
tQH - tDQSQ
tCH, tCL
–
–
6.0
–
6.5
1.0
–
1.3
–
0.75
1.25
0.2
–
0.2
–
tQH - tDQSQ
tCH, tCL
–
–
7.0
–
7.0
1.0
–
1.5
–
t
tDQSS
-10
t
Units
Notes
ns
7
ns
7
t
CK
CK
t
CK
t
ns
ns
ns
ns
tCK
tCK
ns
38
23, 28, 37
23, 28, 37
39
22, 23
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
22
29
15, 33
15
14, 37
IHS
1.5
–
1.7
–
ns
14, 37
tIS
F
1.3
–
1.5
–
ns
14, 37
t
ISS
1.5
–
1.7
–
ns
14, 37
tIPW
3.0
2
t
HP
-tQHS
–
45
75
–
–
–
–
–
–
ns
39
tCK
ns
22, 23
0.75
70,000
–
3.4
2
t
HP
-tQHS
–
50
80
1
70,000
–
ns
ns
ns
30
22.5
–
97.5
22.5
–
15.6
–
–
30
–
80
30
–
15.6
–
–
ns
µs
ns
ns
20
35
tMRD
t
QH
tQHS
tRAS
t
RC
tRCD
tREFI
tRFC
tRP
50
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
Electrical Specifications
Table 15:
Electrical Characteristics and Recommended AC Operating Conditions (continued)
Notes: 1–6, 27; notes appear on pages 52–54; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
-75
Parameter
Symbol
DQS read preamble
t
CL = 3
CL = 2
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE to READ command delay
Exit power-down mode to first valid command
Exit SELF REFRESH to first valid command
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
Min
RPRE(3)
RPRE(2)
t
RPST
t
RRD
t
WPRE
t
WPRES
tWPST
tWR
tWTR
tXP
tXSR
0.9
0.5
0.4
15
0.25
0
0.4
15
1
8.8
120
t
51
-10
Max
1.1
1.1
0.6
–
–
–
0.6
–
–
–
–
Min
0.9
0.5
0.4
15
0.25
0
0.4
15
1
25
120
Max
1.1
1.1
0.6
–
–
–
0.6
–
–
–
–
Units
t
CK
CK
t
CK
ns
t
CK
ns
tCK
ns
tCK
ns
ns
t
Notes
33
33
17, 18
16
41
40
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Notes
Notes
1. All voltages referenced to Vss.
2. All parameters assume proper device initialization.
3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage range specified.
4. Outputs measured with equivalent load:
50
I/O
20 pF
Full-drive strength
50
I/O
10 pF
Half-drive strength
50
I/O
5 pF
Quarter-drive strength
5. Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment,
but input timing is still referenced to VDDQ/2 (or to the crossing point for CK/CK#).
The output timing reference voltage level is VDDQ/2.
6. All AC timings assume an input slew rate of 1V/ns.
7. CAS latency definition: for CL = 2, the first data element is valid at (tCK + tAC) after the
clock at which the READ command was registered; for CL = 3, the first data element is
valid at (2 × tCK + tAC) after the first clock at which the READ command was
registered.
8. VID is the magnitude of the difference between the input level on CK and the input
level on CK#.
9. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must
track variations in the DC level of the same.
10. IDD is dependent on cycle rate, and may be affected by output loading if VDD and
VDDQ are supplied from the same source. Specified values are obtained with minimum cycle time for CL = 3 with the outputs open.
11. Enables on-chip refresh and address counters.
12. IDD specifications are tested after the device is properly.
13. This parameter is sampled. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, f = 100 MHz,
TA = 25ºC, VOUT(DC) = VDDQ/2, VOUT (peak-to-peak) = 0.2V. DM input is grouped with
I/O balls, reflecting the fact that they are matched in loading.
14. Fast command/address input slew rate ≥ 1V/ns. Slow command/address input slew
rate ≥ 0.5V/ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an
additional 50ps per each 100mV/ns reduction in slew rate from the 0.5V/ns. tIH
remains constant.
15. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (HZ) or begins driving (LZ).
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
52
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Notes
16. The maximum limit for this parameter is not a device limit. The device will operate
with a greater value for this parameter, but system performance (bus turnaround) will
degrade accordingly.
17. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
18. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command.
19. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the
minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS.
20. The refresh period equals 64ms. This equates to an average refresh rate of 15.625µs.
21. The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
22. The valid data window is derived by achieving other specifications: tHP (tCK/2),
t
DQSQ, and tQH (tHP - tQHS). The data valid window derates directly proportional
with the clock duty cycle and a practical data valid window can be derived. The clock
is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when
operating beyond a 45/55 ratio.
23. Referenced to each output group: LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.
24. This limit is a nominal value and does not result in a fail. CKE is HIGH during
REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby).
25. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC), or VIH(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).
26. The input capacitance per ball group will not differ by more than this maximum
amount for any given device.
27. CK and CK# input slew rate must be ≥ 1V/ns (2V/ns if measured differentially).
28. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If
the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be
added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds
4V/ns, functionality is uncertain.
29. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the
device CK and CK# inputs, collectively.
30. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN)
can be satisfied prior to the internal PRECHARGE command being issued.
31. Any positive glitch must be less than 1/3 of the clock cycle and not more than +200mV
or 2.0V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle
and not exceed either -150mV or 1.6V, whichever is more positive.
32. VIH overshoot: VIH (MAX) = VDDQ + 0.5V for a pulse width ≤ 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -0.5V for a
pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.
33. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition.
34. IDD2N specifies DQ, DQS, and DM to be driven to a valid HIGH or LOW logic level.
35. CKE must be active (HIGH) during the entire time a REFRESH command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tRFC later.
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
53
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Notes
36. Values for IDD6 85°C are guaranteed for the entire temperature range. All other IDD6
values are estimated.
37. The transition time for input signals (CAS#, CKE, CS#, DM, DQ, DQS, RAS#, WE#, and
addresses) are measured between VIL(DC) to VIH(AC) for rising input signals and
VIH(DC) to VIL(AC) for falling input signals.
38. tDAL = (tWR/tCK) + (tRP/tCK): for each term, if not already an integer, round to the
next higher integer.
39. These parameters guarantee device timing but they are not necessarily tested on each
device.
40. Clock must be toggled a minimum of two times during this period.
41. Clock must be toggled a minimum of one time during this period.
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Timing Diagrams
Timing Diagrams
Figure 31:
x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window
CK#
CK
T1
T2
tHP5
tHP5
T2n
T3
tHP5
tDQSQ3
tHP5
T3n
tHP5
tDQSQ3
T4
tHP5
tDQSQ3
tDQSQ3
LDQS1
tQH4
tQH4
tQH4
Lower Byte
DQ (Last data valid)2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ (First data no longer valid)2
tQH4
DQ (Last data valid)2
T2
T2n
T3
T3n
DQ (First data no longer valid)2
T2
T2n
T3
T3n
DQ0 - DQ7 and LDQS, collectively6
T2
T2n
T3
T3n
Data Valid
window
Data Valid
window
Data Valid
window
tDQSQ3
Data Valid
window
tDQSQ3
tDQSQ3
tDQSQ3
UDQS1
tQH4
tQH4
tQH4
Upper Byte
DQ (Last data valid)7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ (First data no longer valid)7
tQH4
valid)7
T2
T2n
DQ (First data no longer valid)7
T2
T2n
DQ8 - DQ15 and UDQS, collectively6
T2
T2n
T3
T3n
Data Valid
window
Data Valid
window
Data Valid
window
Data Valid
window
DQ (Last data
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
T3
T3
T3n
T3n
1. DQ transitioning after DQS transition define tDQSQ window. LDQS defines the lower byte
and UDQS defines the upper byte.
2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with
DQS transition and ends with the last valid DQ transition.
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transition and is tQH minus tDQSQ.
7. DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, or DQ15.
55
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Timing Diagrams
Figure 32:
Data Output Timing – tAC and tDQSCK
T0
T1
T2
READ
NOP
NOP
T3
T2n
T3n
T4
T4n
T5
T5n
T6
CK#
CK
COMMAND
NOP
NOP
NOP
tDQSCK
(MAX)
tDQSCK
(MAX)
CL = 3
NOP
tRPST
tRPRE
DQS, or LDQS/UDQS1
tAC (MAX)
All DQ values, collectively2
T2
T2n
T3
T3n
T4
T4n
T5
T5n
tHZ (MAX)
Notes:
Figure 33:
1.
2.
3.
DQ transitioning after DQS transition define tDQSQ window.
All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
tAC is the DQ output window relative to CK, and is the “long term” component of DQ skew.
Data Input Timing
T03
T1
T1n
T2
T2n
T3
CK#
CK
tDQSS
tDSH1 tDSS2
tDSH1 tDSS2
DQS4
tDQSL tDQSH tWPST
tWPRES tWPRE
DI
b
DQ
DM5
tDS
tDH
TRANSITIONING DATA
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
1.
2.
3.
4.
5.
tDSH
(MIN) generally occurs during tDQSS (MIN).
DSS (MIN) generally occurs during tDQSS (MAX).
WRITE command issued at T0.
LDQS controls the lower byte and UDQS controls the upper byte.
LDM controls the lower byte and UDM controls the upper byte.
t
56
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Timing Diagrams
Figure 34:
Initialize and Load Mode Registers
((
))
VDD
((
))
VDDQ
T1
T0
CK#
((
))
((
))
CK
LVCMOS
HIGH LEVEL
CKE
tCH
((
))
((
))
NOP2
DM
tCL
((
))
((
))
tIS
COMMAND1
Ta0
Tb0
Tc0
Tf0
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tIH
NOP
((
))
((
))
PRE
tCK
((
))
((
))
AR
AR
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
ALL BANKS
((
))
((
))
A10
Te0
((
))
((
))
tIS
tIH
((
))
((
))
LMR
LMR
((
))
((
))
tIS
Addresses
Td0
((
))
((
))
((
))
((
))
((
))
((
))
NOP3
((
))
((
))
((
))
((
))
CODE
((
))
((
))
RA
((
))
((
))
((
))
((
))
CODE
((
))
((
))
RA
((
))
((
))
((
))
((
))
BA0 = L,
BA1 = H
((
))
((
))
BA
((
))
((
))
tIH
CODE
tIS
ACT
tIH
CODE
tIS
((
))
((
))
tIH
Bank Address
(BA0, BA1)
((
))
((
))
DQS
((
))
High-Z
((
))
((
))
((
))
((
))
((
))
((
))
DQ
((
))
High-Z
((
))
((
))
((
))
((
))
((
))
((
))
BA0 = L,
BA1 = L
T = 200µs
tRP4
tRFC4
tRFC4
tMRD4
tMRD4
Power-up: VDD and CK stable
DON’T CARE
Load Standard Mode Register
Load Extended Mode
Register
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
1. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH
command, ACT = ACTIVE command, RA = Row address, BA = Bank address.
2. NOP or DESELECT commands are required for at least 200µs.
3. Other valid commands are possible.
4. NOPs or DESELECTs are required during this time.
57
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Timing Diagrams
Figure 35:
Power-Down Mode (Active or Precharge)
T0
T1
T2
CK#
CK
tCK
tIS
tIH
tCH
tCL
Ta0
tIS
CKE
Ta1
Ta2
((
))
((
))
Tb1
((
))
((
))
tCKE
((
))
((
))
((
))
tXP
tIS
tIH
((
))
((
))
VALID
((
))
((
))
((
))
((
))
VALID
DQS
((
))
((
))
((
))
((
))
DQ
((
))
((
))
((
))
((
))
DM
((
))
((
))
((
))
((
))
COMMAND
VALID1
tIS
ADDR
NOP
tIH
VALID
((
))
((
))
NOP
NOP
Must not exceed Refresh device limits
Enter 2
Power-Down
Mode
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
Exit3
Power-Down
Mode
DON’T CARE
1. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at
least one row is already active), then the power-down mode shown is active power-down.
2. No column accesses are allowed to be in progress at the time power-down is entered.
3. There must be at least one clock pulse during tXP time.
58
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Timing Diagrams
Figure 36:
Auto Refresh Mode
T0
T2
T1
T3
T4
CK#
CK
tIS
tIH
CKE
tCL
tIH
NOP 2
PRE
Ta0
Ta1
))
((
))
VALID
tIS
COMMAND1
tCH
CK
((
))
((
))
NOP2
NOP2
AR
))
((
))
((
))
((
))
))
((
))
NOP2, 3
AR 6
((
))
((
))
Tb0
Tb1
Tb2
NOP2
ACT
VALID
NOP2, 3
((
))
((
))
((
))
((
))
RA
((
))
((
))
((
))
((
))
RA
((
))
((
))
((
))
((
))
BA
DQS5
((
))
((
))
((
))
((
))
DQ5
((
))
((
))
((
))
((
))
DM5
((
))
((
))
((
))
((
))
A0–A9, A111
ALL BANKS
A101
ONE BANK
tIS
BA0, BA11
tIH
Bank(s)4
tRP
tRFC
tRFC6
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row address, BA = Bank
address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at
these times. CKE must be active during clock positive transitions.
3. NOP or COMMAND INHIBIT are the only commands allowed until after tRFC time, CKE must
be active during clock positive transitions.
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active
(i.e., must precharge all active banks).
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
6. The second AUTO REFRESH is not required and is only shown as an example of two back-toback AUTO REFRESH commands.
59
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©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Timing Diagrams
Figure 37:
Self Refresh Mode
T0
T1
CK#
CK1
tCH
tIS
tIH
tCL
COMMAND4
Ta1
tCK
AR
((
))
((
))
((
))
((
))
Tb0
((
))
((
))
((
))
tIH
NOP
Ta0(1)
t IS
tIS
CKE1
tIS
((
))
((
))
NOP
((
))
((
))
ADDR
((
))
((
))
((
))
((
))
DQS
((
))
((
))
((
))
((
))
DQ
((
))
((
))
((
))
((
))
DM
((
))
((
))
((
))
((
))
VALID
tIS
tIH
VALID
tRP2
tXSR3
Enter self refresh mode
Exit self refresh mode
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
1. Clock must be stable before exiting self refresh mode. That is, the clock must be cycling
within specifications by Ta0.
2. Device must be in the all banks idle state prior to entering self refresh mode.
3. NOPs or DESELECT are required for tXSR time with at least two clock pulses.
4. AR = AUTO REFRESH command.
60
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Timing Diagrams
Figure 38:
Bank Read – Without Auto Precharge
CK#
T1
T0
T2
T3
T4
T5
NOP6
PRE7
T5n
T6
T6n
T7
T8
NOP6
ACT
CK
tIS
tIH
tIS
tIH
tCK
tCH
tCL
CKE
COMMAND5
NOP6
NOP6
ACT
tIS
READ2
NOP6
tIH
A0–A9
RA
A11
RA
Col n
RA
RA
tIS
tIH
ALL BANKS
A10
RA
RA
3
ONE BANK
tIS
BA0, BA1
tIH
Bank x
Bank x4
Bank x
Bank x
tRCD
tRP
tRAS7
tRC
DM
CL = 2
Case 1:
tAC
(MIN) and
tDQSCK
(MIN)8
tDQSCK
tRPRE
tRPST
(MIN)
DQS
tLZ
(MIN)
tAC
(MIN)
DOUT
n
DQ1
tLZ
DOUT
n+1
DOUT
n+2
DOUT
n+3
(MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)8
tRPRE
tDQSCK
tRPST
(MAX)
DQS
DOUT
n
DQ1
tAC
(MAX)
DOUT
n+1
DOUT
n+2
DOUT
n+3
tHZ
(MAX)
TRANSITIONING DATA
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
DON’T CARE
1.
2.
3.
4.
5.
6.
DOUT n = data-out from column n.
BL = 4 in the case shown.
Disable auto precharge.
“don’t care” if A10 is HIGH at T5.
RA = row address, BA = bank address, PRE = PRECHARGE, ACT = ACTIVE.
NOP commands are shown for ease of illustration; other commands may be valid at these
times.
7. The PRECHARGE command can only be applied at T5 if tRAS minimum is met.
8. Refer to Figure 31 on page 55 and Figure 32 on page 56 for detailed DQS and DQ timing.
61
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Timing Diagrams
Figure 39:
CK#
Bank Read – with Auto Precharge
T1
T0
T2
T3
T4
T5
T5n
T6
T6n
T7
T8
NOP5
ACT
CK
tIS
tCK
tIH
tCH
tCL
CKE
tIS
COMMAND4
tIH
NOP6
NOP5
ACT
tIS
A0–A9
RA
A11
RA
A10
RA
READ2
NOP5
NOP5
NOP5
tIH
Col n
RA
RA
3
RA
tIS
tIS
BA0, BA1
tIH
tIH
Bank x
Bank x
Bank x
tRCD
tRP
tRAS
tRC
DM
CL = 2
Case 1: tAC (MIN) and tDQSCK (MIN)6
tDQSCK
tRPRE
tRPST
(MIN)
DQS
tLZ
tAC
(MIN)
(MIN)
DOUT
n
DQ1
tLZ
DOUT
n+1
DOUT
n+2
DOUT
n+3
(MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)6
tRPRE
tDQSCK
(MAX)
tRPST
DQS
DOUT
n
DQ1
tAC
(MAX)
DOUT
n+1
DOUT
n+2
DOUT
n+3
tHZ
(MAX)
TRANSITIONING DATA
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
DON’T CARE
1.
2.
3.
4.
5.
DOUT n = data-out from column n.
BL = 4 in the case shown.
Enable auto precharge.
PRE = PRECHARGE, ACT = ACTIVE, RA = Row address, BA = Bank address.
NOP commands are shown for ease of illustration; other commands may be valid at these
times.
6. Refer to Figure 31 on page 55 and Figure 32 on page 56 for detailed DQS and DQ timing.
62
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Timing Diagrams
Figure 40:
Bank Write – Without Auto Precharge
T1
T0
CK#
T2
CK
tIS
tIH
tIS
tIH
tCK
T3
tCH
T4
T4n
T5
T5n
T6
T7
T8
NOP6
NOP6
PRE
tCL
CKE
COMMAND5
NOP6
NOP6
ACT
tIS
A0-A9
NOP6
NOP6
WRITE2
tIH
RA
Col n
RA
A11
tIS
A10
RA
tIS
BA0, BA1
tIH
ALL BANKS
3
ONE BANK
tIH
Bank x
Bank x4
Bank x
tWR
tRCD
tRP
tRAS
tDQSS(NOM)
DQS
tDQSL
tWPRES tWPRE
tDQSH tWPST
DI
b
DQ1
DM
tDS
tDH
TRANSITIONING DATA
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
1.
2.
3.
4.
5.
6.
DI b = data-out from column n.
BL = 4 in the case shown.
Disable auto precharge.
“Don’t Care” if A10 is HIGH at T5.
PRE = PRECHARGE, ACT = ACTIVE, RA = Row address, BA = Bank address.
NOP commands are shown for ease of illustration; other commands may be valid at these
times.
7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T4 or T5.
8. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
63
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Timing Diagrams
Figure 41:
CK#
Bank Write – with Auto Precharge
T1
T0
T2
CK
tIS
tIH
tIS
tIH
tCK
T3
tCH
T4
T4n
T5
T5n
T6
T7
NOP5
NOP5
T8
tCL
CKE
COMMAND4
NOP5
NOP5
ACT
tIS
A0-A9
RA
A11
RA
NOP5
NOP5
WRITE2
NOP5
tIH
Col n
3
A10
RA
tIS
BA0, BA1
tIS
tIH
tIH
Bank x
Bank x
tWR
tRCD
tRP
tRAS
tDQSS (NOM)
DQS
tWPRES tWPRE
tDQSL
tDQSH tWPST
DI
b
DQ1
DM
tDS
tDH
TRANSITIONING DATA
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
1.
2.
3.
4.
5.
DI b= data-out from column n.
BL = 4 in the case shown.
Disable auto precharge.
PRE = PRECHARGE, ACT = ACTIVE, RA = Row address, BA = Bank address.
NOP commands are shown for ease of illustration; other commands may be valid at these
times.
6. tDSH is applicable during tDQSS (MIN) and is referenced from CK T4 or T5.
7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
64
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Timing Diagrams
Figure 42:
CK#
Write – DM Operation
T1
T0
T2
T3
T4
T4n
T5
T5n
T6
T7
T8
NOP6
NOP6
PRE
CK
tIS
tIH
tIS
tIH
tCK
tCH
tCL
CKE
COMMAND5
NOP6
NOP6
ACT
tIS
A0–A9
RA
A11
RA
tIH
Col n
tIS
A10
RA
tIS
BA0, BA1
NOP6
NOP6
WRITE2
tIH
ALL BANKS
3
ONE BANK
tIH
Bank x
Bank x4
Bank x
tWR
tRCD
tRP
tRAS
tDQSS (NOM)
DQS
tDQSL
tWPRES tWPRE
tDQSH tWPST
DI
b
DQ1
DM
tDS
tDH
TRANSITIONING DATA
DON’T CARE
Notes:
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
1.
2.
3.
4.
5.
6.
DI b = data-out from column n.
BL = 4 in the case shown.
Disable auto precharge.
“Don’t Care” if A10 is HIGH at T5.
PRE = PRECHARGE, ACT = ACTIVE, RA = Row address, BA = Bank address.
NOP commands are shown for ease of illustration; other commands may be valid at these
times.
7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T4 or T5.
8. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
65
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
128Mb: 8 Meg x 16 Mobile DDR SDRAM
Package Dimensions
Package Dimensions
Figure 43:
60-Ball VFBGA Package
0.65 ±0.05
SEATING
PLANE
C
0.10 C
60X Ø 0.45
SOLDER BALL
DIAMETER REFERS
TO POST REFLOW
CONDITION. THE PREREFLOW DIAMETER
IS Ø 0.42
SOLDER BALL MATERIAL:
96.5% Sn, 3% Ag, 0.5% Cu (lead-free)
SOLDER BALL PADS:
Ø 0.40 SOLDER MASK DEFINED
SUBSTRATE MATERIAL:
PLASTIC LAMINATE
MOLD COMPOUND:
EPOXY NOVOLAC
6.40
0.80 TYP
BALL A1 ID
BALL A1 ID
5.00 ±0.05
BALL A1
BALL A9
CL
7.20
3.60
10.00 ±0.10
0.80 TYP
CL
3.20
1.00 MAX
4.00 ±0.05
8.00 ±0.10
Notes:
1. Dimensions are in millimeters.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth
herin. Although considered final, these specifications are subject to change, as further product development and data
characterization sometimes occur.
PDF: 09005aef8199c1ec/Source: 09005aef81a19319
MT46H8M16LF_1.fm - Rev. K 7/07 EN
66
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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